The present invention relates to a frequency divider having a division factor of an odd number applied to semiconductor integrated circuits such as microcomputers.
In semiconductor integrated circuits such as microcomputers, a given clock is subjected to frequency multiplication in a PLL or the like or frequency division in a frequency divider to generate a desired clock signal. In these frequency dividers, an output having a duty of 50% obtained by frequency division with a division factor of an odd number is demanded in many cases.
In a conventional art, a complicated circuit that encodes a counter output and conducts necessary frequency division is used in order to implement a frequency divider having a division factor of an odd number and a duty different from 50% or, a frequency divider having a division factor of an odd number and a duty of 50%. Thus, there is a problem that the circuit scale is large and high speed operation is difficult.
FIG. 23 shows a configuration of a conventional frequency divider having a division factor of an odd number. In this conventional art, a division generation section 102 having a division factor of an odd number encodes outputs of 2N-counters 100 and 101 and conducts reset control on the 2N-counters 100 and 101 to produce a frequency division output with a division factor of N and a duty of 50%. In this conventional art, however, a logic circuit which encodes and resets counter is needed. Therefore, the circuit scale becomes large, and restrictions to the clock capable of being subject to frequency division become stricter.
In an N-stage Johnson counter formed of 2N flip-flops (F1 to F2N) explained in Japanese Patent Application Laid-Open No. 7-321642, a data output Q of a flip-flop at each stage except a final stage is input to a data input D of a flip-flop at its subsequent stage. In addition, an inverted data output QB of a flip-flop (F2N) at the final stage is connected to a data input D of a flip-flop (F1) at a first stage. A normal signal of a master clock CIN having a duty of 50% is input to clock inputs C of flip-flops at odd-numbered stages. An inverted signal of the master clock CIN is input to clock inputs C of flip-flops at even-numbered stages. Flip-flops of two stages forma Johnson counter of one stage. A first AND gate performs an AND-ing function on a data output Q of the flip-flop (FN) at an Nth stage and a data output Q of the flip-flop (F2N) at a 2Nth stage. A second AND gate performs an AND-ing function on an inverted data output QB of the flip-flop (FN) at the Nth stage and an inverted data output QB of the flip-flop (F2N) at the 2Nth stage. An OR gate performs an OR-ing function on outputs of the first AND gate and the second AND gate. A frequency division output with a division factor of N and a duty of 50% is obtained from an output of the OR gate. For example, if 2N=6, a frequency division output with a division factor of 3 can be obtained.
When frequency division with a division factor of 3 is conducted, the conventional art needs Johnson counters of three stages, i.e., flip-flop circuits of six stages. The number of stages of flip-flops increases, and the circuit scale becomes large. This results in a problem that it is difficult to cope with high speed operation.
It is an object of the present invention to provide a frequency divider capable of providing a frequency division signal having an arbitrary frequency division factor that includes a division factor of an odd number at a small circuit scale, and capable of operating at a high speed.
The frequency divider according to this invention comprises a storage having a plurality of serially-connected storage units which temporarily hold data input based on a control by an input control signal, in which a data output of each storage unit is input to an immediately subsequent storage unit. This frequency divider also comprises a clock inversion circuit which is supplied with an output of a final storage unit in the storage and a clock signal of original oscillation, inverts logic of the clock signal at timing of a change of the output of the final storage unit, and supplies the logic inverted clock signal to odd-numbered storage units and even-numbered storage units in a complementary manner as an input control signal. This frequency divider further comprises an inversion-delay circuit which inverts logic of the output of the final storage unit, provides the output of the final storage unit with a predetermined delay, and inputs the delayed output to a data input of a first storage unit in the storage.
Other objects and features of this invention will become understood from the following description with reference to the accompanying drawings.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.